1. Technical Field
The present invention relates generally to the field of semiconductor processing and, more specifically, to multiple-plane FinFET CMOS.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in complementary metal oxide semiconductor (CMOS) technologies, such as in the design and fabrication of field effect transistors (FETs). FETs are the basic electrical devices of today""s integrated circuits and are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.). FETs may be formed on conventional substrates. For example, a conventional CMOS FET formed on a silicon wafer may include a gate oxide layer formed on the wafer, a gate formed on the gate oxide layer, spacers formed beside the gate on the gate oxide layer, and doped source/drain (S/D) regions arranged on respective sides of a gate conductor. The gate is separated from a channel (which is situated between the S/D regions) by the gate oxide layer. Shallow trench insulator (STI), local oxidation of silicon (LOCOS), or poly-buffered LOCOS isolations are usually employed to provide for isolation of adjacent transistors. When the FET is operated, an electric field is generated by applying a voltage to the gate. The electrical field is used to control the channel situated between the S/D regions. For example, if the channel is turned on, the electrons flow from the source region to the drain region. In contrast, if the channel is turned off, the electrons cannot flow between the source region and the drain region. Therefore, the on or off state of the channel controls the connection or disconnection of the circuit.
Unfortunately, increased device density in CMOS technologies often results in degradation of performance and/or reliability. One type of FET that has been proposed to facilitate increased device density is a double gated FET (FinFET). FinFETs use two gates, one on each side of a fin body (i.e. transistor body), to facilitate scaling of CMOS dimensions, while maintaining an acceptable performance. In particular, the use of the double gate suppresses Short Channel Effects (SCE), provides for lower leakage, and provides for more ideal switching behavior. In addition, the use of the double gate increases gate area, which allows the FinFET to have better current control, without increasing the gate length of the device. As such, the FinFET is able to have the current control of a larger transistor without requiring the device space of the larger transistor.
Another way to facilitate scaling of CMOS dimensions, while maintaining an acceptable performance, is to increase the mobility of carriers in a semiconductor material. In CMOS technology, n-channel FETs use electrons as carriers and p-channel FETs use holes as carriers. When an electric field is applied to a semiconductor substrate, each of the carriers (i.e. holes and electrons) in the substrate will experience a force from the field and will be accelerated along the field in the opposite direction of the field. The velocity of the carriers due to this effect is called drift velocity and it is proportional to the applied electric field. This proportionality factor is known as mobility (xcexc). The higher the mobility, the higher the current density the transistor will have, resulting in a faster the switching speed.
In conventional CMOS technologies, mobility of carriers is dependent on a number of factors, especially the surface plane of a wafer. That is, carriers see the periodicity of the atoms (the pattern the atoms form), which is completely determined by the crystal plane. Thus, planar devices always have the mobility associated with the plane on which they are formed, and rotating planar FET designs formed on the same crystal plane has no mobility effect.
Accordingly, conventional CMOS technologies use silicon substrates having a surface oriented on a (100) crystal plane. Conventional silicon substrates having a surface oriented on the (100) crystal plane are chosen because: (a) the surface state density between the silicon substrate and the silicon oxide film is at a minimum when the silicon substrate surface is oriented on the (100) plane; and (b) the mobility of electrons in the (100) plane is higher than in other crystal planes, and therefore, the source-drain current of a n-channel FET formed on the semiconductor substrate having the (100) plane provides the largest current. However, the mobility of holes is not optimized in the (100) plane, and therefore, the source-drain current of a p-channel FET formed on the semiconductor substrate having the (100) plane is inevitably small. The p-channel FET therefore fails to have desirable characteristics, even though the n-channel FET exhibits good characteristics. Hole mobility could be enhanced, especially at high electric fields, if p-channel FETs were formed on the (111) plane. However, because the (111) plane has a worse mobility for electrons, it is not used in conventional planar CMOS. In conventional planar CMOS, since utilizing different planes for different devices is impossible (i.e. since planar CMOS is xe2x80x9cplanarxe2x80x9d, both n-channel FETs and p-channel FETs must be on the same plane), the (100) plane provides a compromise between maximizing hole and electron mobilities.
Thus, there is a need for improved CMOS technologies utilizing various crystal planes for FET current channels in order to optimize mobility and/or reduce mobility in specific devices depending upon the particular application, thereby maintaining an acceptable and/or desired CMOS performance.
In contrast to conventional planar complementary metal oxide semiconductor (CMOS) technologies, namely in the design and fabrication of field effect transistors (FETs), the present invention may provide CMOS FinFETs on the same substrate utilizing various crystal planes for FET current channels without any complex device engineering. Additionally, since rotating a FinFET design according to the present invention, unlike rotating planar FET designs, changes the actual planar surface of the device, a mobility change may be realized. Thus, by forming multiple FinFETs on various crystal planes on the same substrate, multiple different carrier mobilities may be realized in order to optimize mobility and/or reduce mobility in specific devices as needed, thereby maintaining an acceptable and/or desired performance.
In association with a first embodiment of present invention, a semiconductor structure may include a substrate having a surface oriented on a first crystal plane that enables subsequent crystal planes for channels to be utilized. A first transistor may be included and may have a first fin body. The first fin body may have a sidewall forming a first current channel. The sidewall of the first fin body may be oriented on a second crystal plane to provide a first carrier mobility. A second transistor may also be included and may have a second fin body. The second fin body may have a sidewall forming a second current channel. The sidewall of the second fin body may be oriented on a third crystal plane to provide a second carrier mobility that is different from the first carrier mobility.
There are many exemplary variations of this first embodiment. Accordingly, in a first variation, the substrate may comprise single crystal silicon and/or the surface may be oriented on a {110} crystal plane. In a second variation, the sidewall of the first fin body may be oriented on a {n n m} plane, where n and m are any integer, and the sidewall of the second fin body may be oriented on a {a a b} plane, where a and b are any integer, such that the {n n m} plane and the {a a b} plane are not equivalent by a symmetry transformation.
In a third variation, the first transistor may be one of a first p-channel FinFET (PFET) and a first n-channel FinFET (NFET), and the second transistor may be one of a second PFET and a second NFET. The sidewall of the first fin body of one of the first PFET and the first NFET may be oriented on a second crystal plane to provide one of an optimized carrier mobility and a non-optimized carrier mobility, and the sidewall of the second fin body of one of the second PFET and the second NFET may be oriented on a third crystal plane to provide one of an optimized carrier mobility and a non-optimized carrier mobility.
Thus, in a fourth variation for example, the sidewall of the first fin body of one of the first PFET and the first NFET may be oriented on one of a {100} crystal plane, a {110} crystal plane, and a {111} crystal plane, and the sidewall of the second fin body of one of the second PFET and the second NFET may be oriented on one of a {100} crystal plane, a {110} crystal plane, and a {111} crystal plane. The {111} crystal plane optimizes carrier mobility for a PFET, and both the {100} crystal plane and the {110} crystal plane optimize carrier mobility for an NFET. On the other hand, the {100} crystal plane reduces carrier mobility for a PFET, and the {111} crystal plane reduces carrier mobility for an NFET.
In association with a second embodiment of present invention, a semiconductor structure may include a chip that may include a first single crystal semiconductor sidewall channel oriented on a first crystal plane. The semiconductor chip may also include a second single crystal semiconductor sidewall channel oriented on a second crystal plane different from the first crystal plane so that the first crystal plane is not equivalent to the second crystal plane by a symmetry transformation.
There are also many exemplary variations of this second embodiment. Accordingly, in a first variation, a first mobility may be associated with the first crystal plane and a second mobility may be associated with the second crystal plane, wherein the first mobility is different from the second mobility. In a second variation, the chip may comprise single crystal silicon and/or may have a surface oriented on a {110} crystal plane.
In a third variation, the first single crystal semiconductor sidewall channel may be part of a first FinFET (e.g. one of a first PFET and a first NFET) and the second single crystal semiconductor sidewall channel may be part of a second FinFET (e.g. one of a second PFET and a second NFET). One of the first PFET and the first NFET may be oriented on a second crystal plane to provide one of an optimized carrier mobility and a non-optimized carrier mobility, and one of the second PFET and the second NFET may be oriented on a third crystal plane to provide one of an optimized carrier mobility and a non-optimized carrier mobility. Thus, in a fourth variation for example, one of the first PFET and the first NFET may be oriented on one of a {100} crystal plane, a {110} crystal plane, and a {111} crystal plane, and one of the second PFET and the second NFET may be oriented on one of a {100} crystal plane, a {110} crystal plane, and a {111} crystal plane.
The present invention may also provide an improved process for fabricating CMOS FinFETs on the same substrate utilizing various crystal planes for FET current channels. In association with an embodiment of present invention, a method for forming a semiconductor structure may include the steps of: providing a substrate having a surface oriented on a first crystal plane that enables subsequent crystal planes for channels to be utilized; forming a first transistor so that a sidewall of a first fin body forms a first current channel and so that the sidewall of the first fin body is oriented on a second crystal plane to provide a first carrier mobility; and forming a second transistor so that a sidewall of a second fin body forms a second current channel and so that the sidewall of the second fin body is oriented on a third crystal plane to provide a second carrier mobility that is different from the first carrier mobility.
There are many exemplary variations of this embodiment. Accordingly, in a first variation, the step of providing a substrate may comprise the step of providing a substrate comprising single crystal silicon and/or having a surface oriented on a {110} crystal plane. In a second variation, the step of forming a first transistor may comprise the step of forming a first transistor so that the sidewall of the first fin body is oriented on a {n n m} plane and n and m are any integer, and the step of forming a second transistor may comprise forming a second transistor so that the sidewall of the second fin body is on a {a a b} plane and a and b are any integer such that the {n n m} plane and the {a a b} plane are not equivalent by a symmetry transformation.
In a third variation, the step of forming a first transistor may comprise the step of forming one of a first PFET and a first NFET, and the step of forming a second transistor may comprise the step of forming one of a second PFET and a second NFET. The step of forming one of a first PFET and a first NFET may comprise forming one of a first PFET and a first NFET so that the sidewall of the first fin body is oriented on a second crystal plane to provide one of an optimized carrier mobility and a non-optimized carrier mobility, and the step of forming one of a second PFET and a second NFET may comprise forming one of a second PFET and a second NFET so that the sidewall of the second fin body is oriented on a third crystal plane to provide one of an optimized carrier mobility and a non-optimized carrier mobility.
Thus, in a fourth variation for example, the step of forming one of a first PFET and a first NFET may comprise forming one of a first PFET and a first NFET so that the sidewall of the first fin body is oriented on one of a {100} crystal plane, a {110} crystal plane, and a {111} crystal plane, and the step of forming one of a second PFET and a second NFET may comprise forming one of a second PFET and a second NFET so that the sidewall of the second fin body is oriented on one of a {100} crystal plane, a {110} crystal plane, and a {111} crystal plane.
The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of the invention, as illustrated in the accompanying drawings.